Compute-in-Memory, Less Data Movement
SRAM digital compute-in-memory brings storage and multiply-accumulate operations together, moving weights closer to compute to reduce data-transfer overhead and improve on-chip efficiency.
CIMEURA® CIMEURA targets on-device and edge AI inference with SRAM-based digital compute-in-memory, bringing storage and multiply-accumulate operations together to reduce data movement. Weight decryption and decompression are integrated into the NPU data path to combine energy efficiency with model-weight protection. Flexible NPU configuration and CIMEURA Studio support different power, compute and chip-integration requirements.
Key Advantages
Energy Efficiency for On-Device & Edge AI
Configure power, compute and on-chip resources for AI inference, from low-power on-device applications to high-performance edge workloads.
Weight Compression & Protection
Weight decryption and decompression are integrated into the inference data path, supplying compute data while protecting model weights.
Supporting Software Platform
CIMEURA Studio supports NPU configuration and IP generation, connecting application requirements to chip design and integration.
A Range of Inference Applications
CIMEURA-L Series
Low-Power On-Device AI
AI inference for low-power always-on and on-device sensing applications with constrained power and on-chip resources.
CIMEURA-E Series
General-Purpose On-Device & Edge AI
Compute for diverse on-device and edge vision applications, balancing inference capability with integration requirements.
CIMEURA-H Series
High-Performance Edge AI
Higher-throughput edge inference for applications with greater compute and data-processing demands.
Software Platform
CIMEURA Studio
Configure NPUs and generate IP for target applications, connecting model-inference needs to chip implementation across power, compute and integration targets.
Discuss Your AI Inference Requirements
Share your application, models and precision, power budget and target chip platform. We will arrange a technical discussion.
