International and Chinese cryptographic standards, from standalone cryptographic engines to integrated security subsystems.
Foresemi DesignHub™ (DH) cryptographic IP serves chip and system designers with international and Chinese cryptographic algorithms, true random number generation, chip identity and security subsystems. Addressing encryption, decryption, digital signatures, key exchange, message authentication and data protection, the portfolio spans low-area to high-throughput implementations. Configurable algorithm combinations, interfaces and memory architectures are complemented by optional protection against physical attacks. Available for ASIC and FPGA integration, the IP supports IoT, storage, communications and automotive applications, with CryptCompiler® enabling product selection and configuration evaluation.
Explore algorithm and interface configurations, and evaluate performance and resource requirements.
RSA · ECC · SM2 · ECDSA · ECDH · ECIES · EdDSA · X25519
RSA 1024–4096 bit, SECP, Brainpool, Curve25519 and binary-field ECC, with big-integer and elliptic-curve operations, signatures, key exchange, encryption and decryption. Optional protection against physical attacks.
AES · SM4 · DES · TDES
ECB · CBC · CFB · OFB · CTR · CMAC · CCM · GCM · GMAC · XTS and other modes. Low-area, pipelined and multicore high-throughput implementations support dedicated DMA and optional protection against physical attacks.
SHA-1 · SHA-2 · SHA-3 · SM3 · MD5 · BLAKE · HMAC
Multiple digest lengths and message-authentication options support integrity checking and digital-signature preprocessing, with dedicated DMA, context management and optional protection against physical attacks.
ZUC · ChaCha12 · ChaCha20 · Poly1305 · SNOW-3G
Encryption and integrity protection for secure communications and continuous data streams, including UEA, UIA, EEA and EIA modes.
Chinese cryptographic standards Level 1 · Level 2 · NIST SP800-90B · AIS20/31
Solutions aligned with international and Chinese random-number standards, including digital standard-cell entropy sources, health monitoring, failure detection and post-processing, with coordinated RTL and software implementations.
Chip identity · Device-unique keys · Key binding · Root of trust
Digital standard-cell, SRAM, analog-circuit and specialized-device approaches support chip identity, device-unique keys, key binding, roots of trust and supply-chain security management.
ML-KEM · ML-DSA · SLH-DSA · FN-DSA
Configurable acceleration for post-quantum key encapsulation and digital signatures, supporting post-quantum applications and system integration.
Arm · RISC-V · Cryptographic services · Key management · Security isolation
A dedicated processor integrates public-key, symmetric, hash and random-number modules for secure boot, firmware verification, authentication, key management and cryptographic offload. Suitable for general-purpose, industrial and automotive MCUs and SoCs, with optional physical-attack protection.
Weight compression · Encryption · Runtime loading · Offline preprocessing
Integrated between the DDR controller and on-chip GPU or NPU, CryptICE coordinates compression, decompression, encryption and decryption of model weights. It increases effective weight delivery at a given DDR bandwidth, reduces plaintext exposure in off-chip storage and transfer, and supports runtime loading and offline preprocessing.
Encryption & decryption · Compression & decompression · Virtualization · Multi-tenancy
Dedicated hardware offloads encryption, decryption, compression and decompression from Arm and RISC-V servers and AI CPUs. Supporting software and virtualization scheduling enable shared acceleration, tenant isolation and integrated hardware-software deployment.
GCM · XTS · DDR · PCIe · CXL
Inline encryption and decryption for high-speed DDR, PCIe and CXL data paths, using GCM and XTS modes with multicore pipelines to protect data during transfer and storage access.
Ethernet · Link-layer protection · Encryption & integrity
Frame-level encryption, decryption and integrity-check acceleration for Ethernet link protection. Supports high-speed integration in switches, routers and automotive Ethernet, with optional protection against physical attacks.
ESP · Transport mode · Tunnel mode · VPN
IPsec data processing and cryptographic acceleration for network-layer security, covering ESP, transport and tunnel modes. Supports secure gateways, VPNs and network equipment, with optional protection against physical attacks.
We support IP selection, architecture configuration, hardware-software integration and custom development around your application, algorithm and standards requirements, performance and area targets, and chip integration needs. Contact us to discuss a cryptographic security solution for your project.
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