CIMEURA® NPU IP for On-Device & Edge AI Inference
CIMEURA combines SRAM digital compute-in-memory with model-weight decryption and decompression to reduce data movement and deliver energy-efficient, secure NPU IP for on-device and edge AI inference.
DH-TMU™ Real-Time Mathematical Acceleration IP
CORDIC and FOC hardware acceleration for motor-control and energy-management MCUs and SoCs, freeing main-core resources for real-time control.
